1. Field of the Invention
The present invention relates to a coefficient multiplier and digital delta-sigma modulator using the same, and more particularly to technology for implementing a coefficient multiplier with a new structure based on a coefficient averaging technique to have a simple hardware constitution and occupy a small chip area in comparison with a coefficient multiplier based on canonical signed digit (CSD) representation.
2. Discussion of Related Art
Digital delta-sigma modulators convert a high-resolution input signal into a low-resolution output signal, include high-resolution information in the output signal through oversampling in return, and output the output signal.
In the chip of such a digital delta-sigma modulator, a digital circuit occupies a considerably larger area than an analog circuit. Since the analog circuit requires a low degree of precision, digital delta-sigma modulators are widely used in low voltage/low power application fields.
FIG. 1 is a block diagram of a conventional third-order digital delta-sigma modulator.
Referring to FIG. 1, the conventional third-order digital delta-sigma modulator includes eleven coefficient multipliers 100, four adders 200, three accumulators 300, and one quantizer 400.
In the digital delta-sigma modulator having the above-mentioned constitution, the coefficient multipliers 100 have a larger number than the adders 200 and the accumulators 300. Also, the coefficient multipliers 100 have a much more complex circuit constitution and much larger chip size than the other components.
In other words, it can be understood that the complexity and chip size of a digital delta-sigma modulator are dependent on the complexity and size of coefficient multipliers.
In general, a general-purpose coefficient multiplier has a complex circuit structure, and occupies a significantly large area when it is implemented as a chip. For this reason, to reduce hardware complexity and a chip size, digital delta-sigma modulators are frequently implemented using a CSD coefficient multiplier instead of a general-purpose coefficient multiplier.
In CSD representation, a coefficient of a multiplier having a constant value is represented as a sum of powers of two. A CSD coefficient multiplier will be described in brief below.
FIG. 2 is a block diagram of a CSD coefficient multiplier 100, and FIG. 3 illustrates a shifter 110 shown in FIG. 2.
As shown in FIG. 2, the CSD coefficient multiplier 100 can be implemented by only shifters 110 and adders 130 due to a coefficient represented as a sum of powers of two. As shown in FIG. 3, the shifter 110 is simply implemented by directly connecting buffers 120.
However, even if a digital delta-sigma modulator is implemented using the CSD coefficient multiplier 100, the coefficient multiplier 100 is still the most complex and occupies the largest area in the entire structure.
Consequently, to implement a digital delta-sigma modulator having a simple structure and small size, a coefficient multiplier that has a simple hardware constitution and occupies a small chip area is needed.